| Name | Version | Summary | date |
|---|---|---|---|
| tsfpga | 12.3.2 | A flexible and scalable development platform for modern FPGA projects | 2024-04-29 14:28:26 |
| pyslang | 6.0 | Python bindings for slang, a library for compiling SystemVerilog | 2024-04-22 03:09:17 |
| hdl-registers | 5.1.3 | An open-source HDL register interface code generator fast enough to run in real time | 2024-04-03 07:05:30 |
| masque | 3.1 | Lithography mask library | 2024-03-31 01:10:08 |
| verilog-pad-analyzer | 0.0.6 | VerilogPADAnalyzer is a Python application designed to analyze and report the | 2024-03-26 11:17:12 |
| hour | day | week | total |
|---|---|---|---|
| 87 | 2245 | 9786 | 203353 |